Field of the Invention
The present invention relates to a wafer processing method by which a wafer having a plurality of division lines formed on a front side thereof and having devices formed in a plurality of regions partitioned by the division lines is divided along the division lines into individual device chips, and the individual device chips are coated with a resin.
Description of the Related Art
In a semiconductor device manufacturing process, a plurality of regions are partitioned by division lines arranged in a crossing pattern on a front side of a substantially circular disk-shaped semiconductor wafer, and devices such as integrated circuits (ICs) and large scale integrations (LSIs) are formed in the thus partitioned regions. The semiconductor wafer thus formed is cut along the division lines, whereby the regions in which the devices are formed are divided from one another, to produce individual device chips. In recent years, packaging technologies have been developed in which a wafer is divided into individual device chips and the individual device chips are coated with a resin. As one of such packaging technologies, a packaging technology called wafer level chip size package (WL-CSP) is disclosed in Japanese Patent Laid-open No. 2006-100535.
In the packaging technology disclosed in Japanese Patent Laid-open No. 2006-100535, a back side of a wafer is coated with a resin, then cut grooves reaching the resin are formed along division lines from the front side of the wafer, and a molding resin is laid on the front side of the wafer to coat each of the device chips, and the molding resin is embedded in the cut grooves. Thereafter, using a cutting blade having a thickness smaller than the width of the cut grooves, the molding resin embedded in the cut grooves is cut to thereby divide the wafer into individual wafer level chip size packages (WL-CSP).
In addition, in order to enhance the processing capability of semiconductor chips such as ICs and LSIs, a semiconductor wafer has been put to practical use in such a form that a functional layer including a low-permittivity insulator film (low-k film) stacked on a front side of a substrate of silicon or the like constitutes a semiconductor device, the low-k film being composed of an inorganic film of SiOF, BSG (SiOB) or the like or an organic film that is a polymer film of polyimide, parylene or the like. As a wafer processing method for manufacturing wafer level chip size packages (WL-CSP) by use of this type of semiconductor wafer, there has been developed a technology that includes the following steps.
(1) At the time of forming the cut grooves along the division lines from the front side of the wafer, a laser beam is applied to the functional layer along the division lines to form laser-processed grooves and thereby to remove the functional layer along the division lines, such that a breaking force of the cutting blade will not reach the devices formed in the functional layer (functional layer removing step).
(2) By use of a first cutting blade having a thickness smaller than the width of the laser-processed grooves formed along the division lines, cut grooves having a depth corresponding to a finished thickness of device chips are formed along the laser-processed grooves from the front side of the wafer (cut groove forming step).
(3) A molding resin is laid on the front side of the wafer and the molding resin is embedded in the cut grooves (molding step).
(4) A protective member is attached to a front side of the molding resin laid on the front side of the wafer, and the back side of the wafer is ground to expose the cut grooves (back grinding step).
(5) A dicing tape is adhered to the back side of the wafer, and the molding resin embedded in the cut grooves is cut by use of a second cutting blade having a thickness smaller than the width of the cut grooves, to thereby divide the wafer into individual wafer level chip size packages (WL-CSP) (dividing step).